1. Field of the Invention
The present invention relates to analog memories and, more particularly, to a method and apparatus for refreshing the volatile memory content of an analog memory.
2. Art Background
One of the most challenging problems faced by massively parallel analog information processing implemented in very large scale integration (VLSI) is the local storage of analog information. In most such applications, the analog information is preferably stored in an analog format providing long-term random-access storage. Examples of VLSI applications where such integrated analog storage is desirable include the storage of programmable analog coefficients for audio and video signal processing, for neural information processing, and for process control. Unlike well developed methods for digital programmable storage by means of SRAM and DRAM technology, the random-access long-term storage of analog information in VLSI has enjoyed little success.
In a typical analog storage system, a voltage level on a capacitor encodes an analog memory value, in a manner generally analogous to the storage of binary information in digital memory. However, drift of the voltage of the capacitor due to leakage and noise typically affects the analog representation much more drastically than similar drift in a digital system affects a binary representation. The drift due to leakage is unavoidable if the storage capacitor is directly accessible for writing, and thereby in ohmic contact with surrounding circuitry. In contrast, a floating-gate storage capacitor, completely insulated by a surrounding oxide, avoids memory degradation due to leakage but precludes direct write-access for programming except by slow electron transport through the oxide.
Most applications requiring direct write-access to analog voltages stored in an array of capacitors in VLSI have conventionally used off-chip digital storage and external D/A conversion to periodically refresh the programmed voltages. For large-scale storage, the off-chip method requires high-bandwidth off-chip communication and extra external components, rendering the off-chip method unacceptably expensive.
Because of the disadvantages of off-chip methods, research has been directed to local storage mechanisms for large-scale integrated programmable analog memories. (See, for example, B. Hochet, "Multivalued MOS Memory for Variable-Synapse Neural Networks," Electronic Letters, vol. 25, pp. 669-670, 1989; B. Hochet, V. Peiris, S. Abdot, and M. J. Declercq, "Implementation of a Learning Kohonen Neuron Based on a New Multilevel Storage Technique," IEEE J. Solid-State Circuits, vol. 26, pp. 262-267, 1991; and E. Vittoz, H. Oguey, M. A. Maher, O. Nys, E. Dijkstra, and M. Chevroulet, "Analog Storage of Adjustable Synaptic Weights," in VLSI Design of Neural Networks, Norwell MA: Kluwer Academic, 1991, pp. 47-63.) The basic technique developed by this research is to quantize the analog values stored in the memory, thereby restricting the range of the analog values to a finite set of discrete levels. The analog values are periodically refreshed towards the nearest discrete level to prevent substantial drift of the values. In this manner, the analog values encode digital information, even though no digital storage is required. Instead, the inherently digital information is stored in analog format on a memory capacitor and is repeatedly retrieved by identifying the nearest discrete level. The quantization provides a certain excursion margin for the memory values between consecutive refresh operations, which retrieve the correct discrete level only as long as the refresh rate is fast enough to counteract the effect of the drift. To ensure that the stored value never deviates from one memory level to another, the expected drift accumulated over one refresh interval should be considerably smaller than the separation between neighboring quantization levels. Accordingly, the maximum number of quantization levels that can be resolved by the analog memory depends on the time scale of the refresh intervals relative to the time scale of nominal voltage drift.
In one implementation of the above-described basic technique, as proposed and demonstrated by Hochet (B. Hochet, "Multivalued MOS Memory for Variable-Synapse Neural Networks," Electronic Letters, vol. 25, pp. 669-670, 1989, and B. Hochet, V. Peiris, S. Abdot, and M. J. Declercq, "Implementation of a Learning Kohonen Neuron Based on a New Multilevel Storage Technique," IEEE J. Solid-State Circuits, vol. 26, pp. 262-267, 1991), a discrete level nearest to a storage value is identified by exhaustive sequential comparison of the storage value with a complete set of the discrete levels. Alternatively, an analog-to-digital-to-analog converter (A/D/A converter) is employed to determine the nearest discrete level without requiring an exhaustive comparison of all discrete levels. An extensive review of such techniques, and other techniques, for refresh in dynamic analog memories can be found in "Analog Memories for VLSI Neurocomputing" by Y. Horio and S. Nakamura in Artificial Neural Networks: Paradigms, Applications and Hardware Implementations from IEEE Press, edited by E. Sanchez-Sinencio and C. Lau, pp. 344-364, 1992. In either case, once the nearest discrete level is identified, the analog value representing the nearest discrete level is used to overwrite the stored analog value, thereby refreshing the analog memory. A primary disadvantage of this method is that a mis-identification of the nearest level, even if such occurs rather rarely, causes unrecoverable loss of information. The loss occurs because the value stored in the memory element is replaced by the value of the identified discrete level, erasing all previous information in the refresh process. Furthermore, the requirement that an analog signal be transmitted to the storage device on each refresh cycle requires significant resources, requiring a stable source continuously and consistently generating the discrete levels in sequence. This adds another source of error, likely causing a mis-identification of the nearest level if a significant offset exists between the actual value of the discrete level and a measured value. Such an offset can result from operation of a buffering (unity gain) amplifier in the refresh loop and also from switch injection noise occurring due to clock feed-through while refreshing the memory.